1) Field of the Invention
This invention relates generally to fabrication of isolation regions in semiconductor devices and more particularly to a method for forming shallow trench isolation (STI) regions having protective oxide liner layers on the trench walls.
2) Description of the Prior Art
There is a challenge to develop new processes to shrink the size of Semiconductor devices. For many years the local oxidation isolation method (LOCOS) and buffered LOCOS method were used to form oxide isolation regions between active areas on a substrate. As device dimensions are scaled down into the submicron regime, the LOCOS processes develop problems from the bird's beak. No matter how the LOCOS processes are modified, the bird beak will limit the devices.
Therefore in sub-quarter micron technology, a new isolation with a totally flat surface called the shallow trench isolation (STI) is used. In shallow trench isolation (STI), a trench is etched into the substrate and a chemical vapor deposition oxide is deposited on the wafer surface and etch back so that the trench is filled.
The inventor has experimented with various methods to improve the STI process. The inventor has found that when a HDPCVD oxide is deposited in the trench that the trench wall and other underlying dielectric layers are damaged by Ar sputtering (from the HDPCVD process). Moreover, the HDPCVD trench fill layer often contains metal contaminates the cause device fails. For these reasons HDPCVD layers are used over metal lines in upper layers, but not in STI applications. HDPCVD has superior trench filling capabilities (ability to fill in very small width trenches) compared to other processes such as low pressure chemical vapor deposition (LPCVD), sub atmospheric chemical vapor deposition (SACVD), Hydrogen-Silsesquioxane spin-on-glass (HSQ-SOG), etc. Therefore, there is a need to develop a STI process using HDPCVD oxide that (1) does not damage the Substrate sidewalls and the SiN masking layer, and (2) allows sub 0.5 micron dimension trench filling.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,614,055 (Fairbairn) that shows a High density plasma CVD and etching reactor that can be used for STI filling. U.S. Pat. No. 5,677,231(Maniar) teaches a trench isolation region (32) that is fabricated to include a trench liner (28) comprised of aluminum nitride. U.S. Pat. No. 5,621,241(Jain) shows a trench filling HDP-SiO.sub.2 and CMP method of filling between conductive lines. U.S. Pat. No. 5,116,779(Iguchi) shows a STI fill process including an oxide and nitride liners.
Nag et al., Comparative Evaluation Of Gap-Fill Dielectrics In STI For Sub-0.25 .mu.M Technologies, IEDM 96- pp. 841 to 844 discusses ICP HDP CVD trench fill techniques.